Previous generations of camera imager sensors have had few and easily resolvable problems with fixed pattern artifacts in the imager resulting from overlying metal layers of interconnect in the device. The previous camera imager sensors did not require lens compensation as the patterning of the metal interconnects was a regular pattern across the entire imager sensor array.
The current generation of an imager sensor, such as a Complimentary Metal Oxide Semiconductor (CMOS) imager sensor, however presents challenges to correct fixed pattern artifacts. In general, a CMOS imager sensor circuit includes a focal plane array of CMOS imager sensor cells (or pixels), each one of the pixels includes a photo-conversion device, e.g., a photogate, photoconductor, or photodiode having an associated charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel may include a transistor for transferring charge from the charge accumulation region to a diffusion node and a transistor for resetting the diffusion node to a predetermined charge level prior to charge transference. The pixel may also include a source follower transistor for receiving and amplifying charge from the diffusion node and an access transistor for controlling the readout of the pixel contents from the source follower transistor. In some arrangements, the transfer transistor is omitted and the charge accumulation region is coupled with the diffusion node.
In a CMOS imager sensor cell, the active elements of a pixel perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of imager charge; (3) transfer of charge to the diffusion node accompanied by charge amplification (where a transfer transistor is used); (4) resetting the diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a reset signal and a signal representing pixel charge from the diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by the source follower output transistor.
Current generations of pixel arrays, such as current CMOS imager sensor arrays, utilize metal and micro lens shifting to boost the response to incident light for pixels located away from the center of the pixel array. This shifting is an increasing continuum from the center of the pixel array out to the sides. The shifting has proven to have positive effects of increasing pixel sensitivity to light as well as a reduction of pixel crosstalk, but at the expense of difficult fixed pattern artifacts. These fixed pattern artifacts are a result of electrical coupling from reset and charge transfer transistors to underlying conductive networks in the pixel, namely the photodiode (PD) and the floating diffusion (FD). One could attempt to shift the overlying metal interconnect lines and route them over non-critical areas outside the PD and FD, but due to the increasingly reducing of pixel sizes, such as 2.2 micron and smaller pixel, the non-critical areas are extremely limited.
“The electrical coupling from reset and charge transfer transistors to lower conductive networks (i.e., parasitic capacitance between overlying level metal and underlying level polysilicon and implant regions) is illustrated in FIG. 1, a simplified illustration of a top-down view depicting an imager sensor pixel segment of a CMOS imager sensor device 100. A typical arrangement of photodiode region 102 resides in silicon substrate 101 and overlying metal 1 line 103 and metal 2 lines 104 that are used to connect to transistor gates (not shown) that control and access the imager sensor pixel, the general layout and function of which are known to those skilled in the art.”
FIG. 2 is a simplified cross-sectional view of FIG. 1 depicting parasitic capacitance that can be present between the overlying metal lines and the photodiode region 102 of the imager sensor pixel 100. As seen in FIG. 2, parasitic capacitance (C1) 205 develops between metal 1 line 103 and photodiode region 102, while parasitic capacitance (C2) 206 develops between metal 2 lines 104 and photodiode region 102. As discussed previously, the parasitic capacitance creates undesirable fixed pattern artifacts.
FIG. 3 is a simplified illustration of a top-down view depicting a backside illumination imager sensor pixel segment of a CMOS imager sensor device 300. A typical arrangement of photodiode region 302 resides in silicon substrate 301 and overlying metal 1 line 303 and metal 2 lines 304 that are used to connect to transistor gates (not shown) that control and access the imager sensor pixel, the general layout and function of which are know to those skilled in the art.
FIG. 4 is a simplified cross-sectional view of FIG. 3 depicting parasitic capacitance that can be present between the overlying metal lines and the backside illumination photodiode region 302 of the imager sensor pixel 300. As seen in FIG. 4, parasitic capacitance (C1) 305 develops between metal 1 line 303 and photodiode region 302, while parasitic capacitance (C2) 306 develops between metal 2 lines 304 and photodiode region 302. As discussed previously, the parasitic capacitance creates undesirable fixed pattern artifacts.
The parasitic capacitance that can form in an imager sensor device, including backside illuminated devices, namely between overlying metal and underlying implanted regions, namely the photodiode (PD) and the floating diffusion (FD), is an area that needs addressed in the CMOS imager sensor industry.
Therefore, what is needed in the art is a means to electrically isolate overlying metals and their associated parasitic capacitance from underlying levels of polysilicon and conductively implanted regions for an imager sensor pixel array.